AI number formats: BF16, FP8, NF4, MXFP4

Every AI number format spends a fixed bit budget on a sign, an exponent that sets range, and a mantissa that sets precision. FP32 and BF16 cover huge ranges, FP16 trades range for precision, FP8 and FP4 squeeze both, and integer and block-scaled formats such as INT4, NF4, MXFP4 and NVFP4 rely on shared scale factors to make tiny codes usable. Here are the exact layouts, limits and typical uses of each.

How bits become numbers

A floating-point value is stored as sign, exponent and mantissa (also called significand or fraction). For normal numbers the value is:

x = (−1)^sign × 2^{exponent − bias} × (1 + mantissa / 2^m)

m is the number of mantissa bits; the bias centres the exponent range on zero. Formats are named ExMy for x exponent bits and y mantissa bits.

Exponent bits buy range: each extra bit roughly doubles the number of powers of two you can reach. Mantissa bits buy precision: with m bits, neighbouring values differ by up to 2^−m relative to their size (2⁻¹⁰ ≈ 0.001 for FP16, 2⁻³ = 0.125 for FP8 E4M3). The largest value follows from the top usable exponent: for FP16, (2 − 2⁻¹⁰) × 2¹⁵ = 65,504.

Integers work differently. An INT8 code is a whole number from −128 to 127, and INT4 runs from −8 to 7. They represent real values only through a scale (and optionally a zero-point): real value ≈ scale × code. The steps are perfectly even, but one scale must cover the largest value in its group, which is why integer formats always come with a granularity: per-tensor, per-channel or per-block. Try it in the quantization playground.

FP32, TF32, FP16 and BF16

FP32 (IEEE single precision, 1-8-23) is the reference: about 7 significant decimal digits and a normal range of roughly 1.2 × 10⁻³⁸ to 3.4 × 10³⁸. Optimiser states and master weights usually stay in FP32.

FP16 (IEEE half precision, 1-5-10) halves memory and keeps 10 mantissa bits, but its 5-bit exponent caps values at 65,504 with a smallest normal of 2⁻¹⁴ ≈ 6.1 × 10⁻⁵. Small gradients underflow, so the mixed-precision recipe of Micikevicius et al. (2017) scales the loss up and keeps an FP32 master copy of the weights.

BF16 (bfloat16, 1-8-7) keeps FP32's 8-bit exponent and cuts the mantissa to 7 bits. It covers essentially the same range as FP32 with much coarser steps (2⁻⁷ ≈ 0.0078 relative). Converting from FP32 amounts to rounding away the low 16 bits, and a study by Intel and Facebook researchers found BF16 training matched FP32 results across vision, speech, language and recommendation workloads without hyperparameter changes. Google's TPUs multiply in BF16 and accumulate in FP32 by default.

TF32 (TensorFloat-32) is a compute mode, not a storage format. Introduced with NVIDIA's Ampere A100, it takes FP32 inputs, rounds the mantissa to 10 bits, keeps the 8-bit exponent and accumulates in FP32: 19 meaningful bits inside a 32-bit container. PyTorch's documentation notes TF32 matmuls on A100 run roughly 7× faster with relative error about two orders of magnitude larger than FP32; its TF32 matmul flag has been off by default since version 1.12.

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FP8: E4M3 vs E5M2

FP8 was proposed by researchers from NVIDIA, Arm and Intel (Micikevicius et al., 2022) and later standardised in the OCP 8-bit floating point (OFP8) specification. Both define the same two encodings:

E4M3 (1-4-3, bias 7): drops infinities and reserves a single mantissa pattern for NaN, which frees the top exponent for ordinary values. Maximum magnitude 448; smallest normal 2⁻⁶; smallest subnormal 2⁻⁹.
E5M2 (1-5-2, bias 15): follows IEEE conventions, with infinities and NaNs. Maximum magnitude 57,344; smallest normal 2⁻¹⁴; smallest subnormal 2⁻¹⁶. Roughly FP16's range with only 2 mantissa bits.

The paper recommends E4M3 for weights and activations and E5M2 for gradients, which need range more than precision. NVIDIA's Transformer Engine calls this the hybrid format: E4M3 forward, E5M2 backward. Inference uses E4M3. E4M3 spans only about 15 powers of two between its smallest normal and largest value (BF16 spans about 254), so every FP8 tensor needs a scale factor, typically chosen from recent absolute maxima ("amax").

Worked example: why FP8 needs scaling

Activations up to 1,200 overflow E4M3 (max 448). Dividing by a per-tensor scale of 4 stores at most 300, which fits. Values near 300 sit in the binade from 256 to 512, where 3 mantissa bits give a step of 256 × 2⁻³ = 32, or 128 in original units after rescaling. That is about 11% of 1,200; the worst-case rounding error is half a step.

Four bits and below: NF4, MX, NVFP4 and ternary

With only 16 codes, where the codes sit and how often the scale changes matter most.

NF4 (4-bit NormalFloat)

NF4, introduced with QLoRA (Dettmers et al., 2023), places its 16 levels at quantiles of a standard normal distribution, normalised to [−1, 1], because trained weights are roughly normal. It is asymmetric so that zero is exact: seven negative levels, zero and eight positive levels, running from −1.0 through −0.6962 and 0.0796 up to 1.0. Each 64-weight block is scaled by its absolute maximum. A 32-bit scale per block adds 32 ÷ 64 = 0.5 bits per weight; QLoRA's double quantization stores the scales in 8 bits, cutting that to 8/64 + 32/(64 × 256) ≈ 0.127 bits. NF4 is a storage format, dequantized to BF16 for compute.

Microscaling (MX) formats

The OCP Microscaling (MX) specification v1.0 (September 2023, from AMD, Arm, Intel, Meta, Microsoft, NVIDIA and Qualcomm) defines formats in which every block of 32 elements shares one 8-bit power-of-two scale stored as E8M0: an exponent with bias 127, no mantissa, and the all-ones code reserved for NaN. The concrete formats:

MXFP8: E4M3 or E5M2 elements (max 448 or 57,344).
MXFP6: E2M3 (max 7.5) or E3M2 (max 28) elements, with no Inf or NaN encodings.
MXFP4: E2M1 elements, whose positive values are 0, 0.5, 1, 1.5, 2, 3, 4 and 6, with no Inf or NaN.
MXINT8: 8-bit two's-complement elements with an implied scale of 2⁻⁶, so the maximum is 127/64 = 1.984375.

The shared scale costs 8 ÷ 32 = 0.25 bits per element, so MXFP4 averages 4.25 bits per value. The spec's reference conversion takes the largest power of two not above the block's maximum magnitude and divides it by the element type's largest power of two.

Worked example: one MXFP4 block

Suppose a block's largest magnitude is 0.7. The largest power of two not above 0.7 is 0.5, and E2M1's is 4, so the shared scale is 0.5 ÷ 4 = 2⁻³ = 0.125. Then 0.7 / 0.125 = 5.6 rounds to 6 and decodes to 0.75, while 0.1 / 0.125 = 0.8 rounds to 1 and decodes to 0.125. Coarse, but the scale costs only 8 bits for all 32 values.

NVFP4

NVFP4, introduced with NVIDIA's Blackwell architecture, also uses E2M1 elements but scales differently: blocks of 16 values share an FP8 E4M3 scale, and one FP32 scale per tensor keeps the block scales within E4M3's range. A non-power-of-two scale fits each block's maximum more tightly than E8M0, and smaller blocks adapt to local outliers. Overhead is 8 ÷ 16 = 0.5 bits, about 4.5 bits per value in total.

Ternary and 1.58-bit weights

BitNet b1.58 (Ma et al., 2024) restricts every weight to {−1, 0, +1}. Three states carry log₂(3) ≈ 1.58 bits of information, hence the name. Weights are divided by their mean absolute value and rounded to the nearest level; activations use 8 bits with per-token scaling. Crucially, the model is trained this way from scratch, not quantized afterwards. The paper reports matching a full-precision LLaMA baseline in perplexity from 3B parameters, and a follow-up released BitNet b1.58 2B4T, an open-weight 2B-parameter model trained on about 4 trillion tokens. Ternary weights make matrix multiplication almost multiplication-free, which is why the authors call for dedicated hardware. Five ternary values can be packed into one byte (3⁵ = 243 ≤ 256), or 1.6 bits per weight.

Format reference table

Block formats show element limits; the shared scale sets the actual range.
Format	Bits (sign-exp-mantissa)	Largest value	Smallest normal or nonzero	Relative step	Typical use
FP32	1-8-23	≈3.4 × 10³⁸	≈1.2 × 10⁻³⁸	2⁻²³	Master weights, optimiser state, reference
TF32	1-8-10 (19 of 32 bits)	≈3.4 × 10³⁸	≈1.2 × 10⁻³⁸	2⁻¹⁰	Tensor-core math on FP32 inputs
BF16	1-8-7	≈3.4 × 10³⁸	≈1.2 × 10⁻³⁸	2⁻⁷	Training and serving LLMs
FP16	1-5-10	65,504	≈6.1 × 10⁻⁵	2⁻¹⁰	Inference, mixed precision with loss scaling
FP8 E4M3	1-4-3	448	2⁻⁶	2⁻³	Weights and activations; inference
FP8 E5M2	1-5-2	57,344	2⁻¹⁴	2⁻²	Gradients in FP8 training
INT8	8-bit integer	127 × scale	1 × scale (uniform)	Uniform steps	Weights and activations, edge and server inference
INT4	4-bit integer	7 × scale	1 × scale (uniform)	Uniform steps	Weight-only LLM quantization (GPTQ, AWQ)
NF4	16 normal quantiles	1.0 × block absmax	≈0.08 × absmax	Non-uniform	QLoRA base weights
MXFP6	E2M3 or E3M2 + E8M0 per 32	7.5 or 28 × scale	1 or 0.25 × scale	2⁻³ or 2⁻²	Low-precision training and inference
MXFP4	1-2-1 + E8M0 per 32	6 × scale	1 × scale	2⁻¹	4-bit weights and activations
NVFP4	1-2-1 + E4M3 per 16 + FP32 per tensor	6 × scales	1 × scales	2⁻¹	4-bit inference and training on Blackwell
Ternary	{−1, 0, +1}	1 × scale	1 × scale	—	Natively trained 1.58-bit LLMs

For GGUF block types and more, see the formats atlas.

Hardware support by generation

A format speeds up compute only when the hardware has native instructions for it; otherwise it saves memory but is widened for the arithmetic. Key milestones:

NVIDIA Volta (V100): first Tensor Cores, FP16 inputs with FP32 accumulation.
NVIDIA Ampere (A100): introduces TF32 and supports BF16 alongside FP16 and INT8.
NVIDIA Hopper (H100) and Ada Lovelace: FP8 E4M3 and E5M2. NVIDIA introduced FP8 with H100; vLLM lists FP8 compute for compute capability 8.9 and above, which includes Ada.
NVIDIA Blackwell: adds NVFP4 and MXFP8; Blackwell Ultra's Tensor Cores are described as optimised for FP8, FP6 and NVFP4.
AMD Instinct MI300 (CDNA 3): FP8, BF16, FP16 and INT8 matrix math. MI350 (CDNA 4) adds MXFP8, MXFP6 and MXFP4.
Google TPUs: BF16 multiplication with FP32 accumulation by default.

Try it: Quantization playground

Quantize a signal or a weight distribution to 1–16 bits and watch the error, histogram and SQNR change live.

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Key takeaways

Exponent bits set range, mantissa bits set precision; BF16 keeps FP32's range, FP16 keeps more precision.
FP8 E4M3 tops out at 448 and suits weights and activations; E5M2 reaches 57,344 and suits gradients.
Integer and 4-bit formats only work with scales, and finer scaling granularity costs extra bits per value.
MX formats share an 8-bit power-of-two scale per 32 elements; NVFP4 uses an E4M3 scale per 16 plus a per-tensor FP32 scale.
Ternary 1.58-bit models must be trained that way from scratch; they are not a post-training shortcut.

Frequently asked questions

Is BF16 better than FP16?

For training, usually yes, because its FP32-sized range avoids overflow and underflow without loss scaling. FP16 has three more mantissa bits, so it is more precise for values that stay within its range.

Why is the maximum FP8 E4M3 value 448 and not 240?

An IEEE-style E4M3 would reserve the top exponent for infinities and NaN, capping it at 1.875 × 2⁷ = 240. The FP8 definition drops infinities and keeps one NaN mantissa pattern, so the top exponent holds ordinary values up to 1.75 × 2⁸ = 448.

What is the difference between MXFP4 and NVFP4?

Both use E2M1 elements. MXFP4 shares an E8M0 power-of-two scale per 32 values (about 4.25 bits per value); NVFP4 uses an FP8 E4M3 scale per 16 values plus a per-tensor FP32 scale (about 4.5 bits per value).

Is NF4 faster than INT4?

Not inherently. NF4 is a lookup-based storage format dequantized for compute; its advantage is accuracy on normally distributed weights.

Can I convert an existing model to 1.58-bit?

Not well by simple post-training rounding. BitNet b1.58 models are trained ternary from the start.

Sources and further reading

FP8 Formats for Deep Learning (Micikevicius et al.) — E4M3 and E5M2 definitions and recommended use.
OCP Microscaling Formats (MX) v1.0 specification — MXFP8, MXFP6, MXFP4, MXINT8 and the E8M0 scale.
Introducing NVFP4 (NVIDIA Technical Blog) — two-level scaling and comparison with MXFP4.
Transformer Engine FP8 primer — hybrid FP8 usage, delayed scaling, MXFP8 and NVFP4.
QLoRA: Efficient Finetuning of Quantized LLMs — NF4 construction and double quantization.
The Era of 1-bit LLMs: All Large Language Models are in 1.58 Bits — BitNet b1.58.
Mixed Precision Training (Micikevicius et al.) — FP16 training with loss scaling.
A Study of BFLOAT16 for Deep Learning Training — BF16 versus FP32 across workloads.
PyTorch CUDA semantics: TensorFloat-32 — TF32 defaults and accuracy trade-off.
AMD Instinct MI350 Series microarchitecture — OCP MX format support on CDNA 4.

About this guide. Written and fact-checked by the Quantization.com editorial team against the primary sources listed above. Spotted an error or an outdated command? Send a correction — we fix verified issues within a few days. See our editorial policy.